Wafer Signature Analysis
نویسندگان
چکیده
Continuous scaling of transistor geometries increases leakage current exponentially. This makes differentiating faulty and fault-free chips extremely difficult. The concept of wafer signature is proposed. A wafer signature is obtained by sorting all IDDQ readings on a wafer for a vector. A break or jump in the wafer signature is considered to indicate defective chips. The use of wafer signatures is evaluated for differentiating faulty and faultfree chips using industrial test data.
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